The present invention relates to a semiconductor memory device and, in particular, relates to such a memory device which has a self diagnosis function.
A large capacity semiconductor memory device, for instance, 256 kbit static memory, and 1 Mbit dynamic memory, has recently been developed and reflects the development of the semiconductor producing process. However, due to the complicated structure and the large scale of a memory array in a semiconductor memory device, it has been difficult to manufacture a semiconductor memory device which has no defective cells.
If a complete semiconductor memory device which has no defective cells is desired, the yield rate of the semiconductor memory device decreases considerably, and therefore, the manufacturing cost would increase.
Accordingly, a semiconductor memory device which has partially defective cells (Partially good memory (PGM), or Mostly good memory (MGM)) have been used to reduce the cost of an electronic system.
Conventionally, each memory cell of a semiconductor memory device is measured beforehand, and the address of a defective cell is memorized in an external CPU control unit of a system, which is programmed so that the address of the defective cell is not used.
FIG. 1 is a block diagram of a prior electronic system in which a semiconductor memory with some defective cells is used.
In the figure, a memory IC chip 16 has a row address driver 1, a row address decoder 2, a memory array 3 which might have some defective cells, a column address driver 4, a column address decoder 5, a multiplexer 6, a data input circuit 7, a data output circuit 8, and a write enabling circuit 9. A CPU memory control circuit 10 has a control circuit 11, an address register 12, an input data register 13, an output data register 14, and a decision circuit 15. Said CPU memory control circuit 10 accomplishes the recognition of a defective cell in a memory chip 16 (step 1) by comparing input data with output data of the selected cell, to store an address of the defective cell (step 2), and writing and/or reading an information in or from a normal cell (step 3).
The input data register 13 in the memory control circuit 10 stores input information to the memory array 3. In reading phase of a memory, when the control circuit 11 selects an address of the memory array 3, the input data register 13 stores a correct input data which is to be stored in said selected address, and simultaneously, the output data register 14 stores the output data D.sub.OUT of the selected address cell.
The decision circuit 15 compares the content of the input data register 13 with the content of the output data register 14, and when those two data do not coincide with each other, the selected address at that time is recognized as a defective address, and said address is stored in the address register 12. The memory chip 16 is used so that the defective address stored in the address register 12 is not accessed.
However, the conventional system in FIG. 1 has the disadvantages that the software or program for recognizing a defective cell in the external CPU memory control circuit 10 is very complicated, and its takes long time to recognize a defective address since the cell must be read out by an external CPU. Accordingly, the reduction of the cost of an electronic system has been impossible although a memory cell with some defective cells has been used.